A symmetrical range controller for phase-locked loop circuits includes a first counter coupled to a first signal line, where the first counter is configured to count state transition edges of the first signal, inhibit logic coupled to the first counter, where the inhibit logic is configured to inhibit an output signal of a second counter in response to a predetermined count of the first counter, and reset logic coupled to the first counter, where the reset logic is configured to reset the second counter in response to a full count of the first counter.