In an LSI implemented by a DMA chip, a BCC check block performs BCC check of cache data each time the cache data is read. In response to a check result indicating whether or not the check is completed, a CM read block turns on a BCC check bit and a BCC error bit of a data-transfer-end notification. Further, an FCC check block performs FCC check of the cache data. In response to a check result indicating whether or not the check is completed, the CM read block turns on an FCC check bit and an FCC error bit of the data-transfer-end notification. When data transfer is finished, the CM read block sends the data-transfer-end notification to a CPU via a descriptor block.