Invention Grant
US07921342B2 Integrated circuit comprising a test mode secured by the use of an identifier, and associated method
有权
包括通过使用标识符保护的测试模式的集成电路以及相关联的方法
- Patent Title: Integrated circuit comprising a test mode secured by the use of an identifier, and associated method
- Patent Title (中): 包括通过使用标识符保护的测试模式的集成电路以及相关联的方法
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Application No.: US11675265Application Date: 2007-02-15
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Publication No.: US07921342B2Publication Date: 2011-04-05
- Inventor: Frédéric Bancel , David Hely
- Applicant: Frédéric Bancel , David Hely
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics SA
- Current Assignee: STMicroelectronics SA
- Current Assignee Address: FR Montrouge
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Agent Lisa K. Jorgenson
- Priority: FR0601304 20060215
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
An electronic circuit includes configurable cells capable of being functionally linked to logic cells with which they cooperate to form at least one logic circuit if a chaining command signal is in a first (inactive) state. The electronic circuit also includes a logic interconnection circuit for performing the following functions if the chaining command signal is in a second (active) state. Functionally connecting the configurable cells in a linear feedback shift register if an authentication signal is in a first state, or functionally connecting the configurable cells in a chain in a predefined order to form a shift register if the authentication signal is in a second state.
Public/Granted literature
- US20070257701A1 INTEGRATED CIRCUIT COMPRISING A TEST MODE SECURED BY THE USE OF AN IDENTIFIER, AND ASSOCIATED METHOD Public/Granted day:2007-11-08
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