Invention Grant
US07921346B2 Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)
有权
阵列内置自检(ABIST)设计/诊断设计(DFT / DFD)的验证
- Patent Title: Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)
- Patent Title (中): 阵列内置自检(ABIST)设计/诊断设计(DFT / DFD)的验证
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Application No.: US12262976Application Date: 2008-10-31
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Publication No.: US07921346B2Publication Date: 2011-04-05
- Inventor: Donato Orazio Forlenza , Orazio Pasquale Forlenza , Bryan J. Robbins , Phong T. Tran
- Applicant: Donato Orazio Forlenza , Orazio Pasquale Forlenza , Bryan J. Robbins , Phong T. Tran
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Dillon & Yudell LLP
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.
Public/Granted literature
- US20100115337A1 VERIFICATION OF ARRAY BUILT-IN SELF-TEST (ABIST) DESIGN-FOR-TEST/DESIGN-FOR-DIAGNOSTICS (DFT/DFD) Public/Granted day:2010-05-06
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