Invention Grant
US07921386B2 Fabrication method for semiconductor device, exposure method, pattern correction method and semiconductor device 失效
半导体器件的制造方法,曝光方法,图案校正方法和半导体器件

  • Patent Title: Fabrication method for semiconductor device, exposure method, pattern correction method and semiconductor device
  • Patent Title (中): 半导体器件的制造方法,曝光方法,图案校正方法和半导体器件
  • Application No.: US12108660
    Application Date: 2008-04-24
  • Publication No.: US07921386B2
    Publication Date: 2011-04-05
  • Inventor: Toshiyuki Ishimaru
  • Applicant: Toshiyuki Ishimaru
  • Applicant Address: JP Tokyo
  • Assignee: Sony Corporation
  • Current Assignee: Sony Corporation
  • Current Assignee Address: JP Tokyo
  • Agency: SNR Denton US LLP
  • Priority: JP2007-117847 20070427
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Fabrication method for semiconductor device, exposure method, pattern correction method and semiconductor device
Abstract:
Disclosed herein is a fabrication method for a semiconductor device, including a lithography step of connecting a plurality of mask patterns to each other to form a pattern image of an area greater than the size of the mask patterns. The lithography step includes the steps of: assuring an overlapping exposure region to be exposed in an overlapping relationship by both of two mask patterns to be connected to each other, carrying out exposure transfer of the pattern portions of the two mask patterns to the overlapping exposure region to form a first measurement mark and a second measurement mark in the overlapping exposure region, and carrying out positional displacement measurement of pattern connection by the two mask patterns based on a manner of combination of main marks and sub marks of the measurement marks formed in the overlapping exposure region.
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