Invention Grant
US07921398B2 System and medium for placement which maintain optimized timing behavior, while improving wireability potential
有权
用于放置的系统和介质,其保持优化的定时行为,同时提高可线性潜力
- Patent Title: System and medium for placement which maintain optimized timing behavior, while improving wireability potential
- Patent Title (中): 用于放置的系统和介质,其保持优化的定时行为,同时提高可线性潜力
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Application No.: US12047382Application Date: 2008-03-13
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Publication No.: US07921398B2Publication Date: 2011-04-05
- Inventor: James J. Curtin , Jose L. Neves , Douglas S. Search
- Applicant: James J. Curtin , Jose L. Neves , Douglas S. Search
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent William A. Kinnaman, Jr.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F19/00

Abstract:
A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.
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