Invention Grant
US07921401B2 Stress analysis method, wiring structure design method, program, and semiconductor device production method
有权
应力分析方法,接线结构设计方法,程序和半导体器件的制造方法
- Patent Title: Stress analysis method, wiring structure design method, program, and semiconductor device production method
- Patent Title (中): 应力分析方法,接线结构设计方法,程序和半导体器件的制造方法
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Application No.: US11703218Application Date: 2007-02-07
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Publication No.: US07921401B2Publication Date: 2011-04-05
- Inventor: Sachiyo Ito , Masahiko Hasunuma , Hisashi Kaneko
- Applicant: Sachiyo Ito , Masahiko Hasunuma , Hisashi Kaneko
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2006-031694 20060208
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F11/22

Abstract:
A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.
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