Invention Grant
US07923338B2 Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence
有权
通过在漏极/源极植入序列期间减小间隔物宽度来增加晶体管中的应力传递效率
- Patent Title: Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence
- Patent Title (中): 通过在漏极/源极植入序列期间减小间隔物宽度来增加晶体管中的应力传递效率
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Application No.: US12271162Application Date: 2008-11-14
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Publication No.: US07923338B2Publication Date: 2011-04-12
- Inventor: Maciej Wiatr , Roman Boschke , Anthony Mowry
- Applicant: Maciej Wiatr , Roman Boschke , Anthony Mowry
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102008016512 20080331
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.
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