Invention Grant
US07923340B2 Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
有权
降低双极晶体管的集电极电阻并集成到标准CMOS流中的方法
- Patent Title: Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
- Patent Title (中): 降低双极晶体管的集电极电阻并集成到标准CMOS流中的方法
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Application No.: US12523368Application Date: 2007-02-14
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Publication No.: US07923340B2Publication Date: 2011-04-12
- Inventor: Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
- Applicant: Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
- Applicant Address: US PA Allentown
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown
- International Application: PCT/US2007/062100 WO 20070214
- International Announcement: WO2008/100312 WO 20080821
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L21/8222
Abstract:
The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
Public/Granted literature
- US20100065920A1 METHOD TO REDUCE COLLECTOR RESISTANCE OF A BIPOLAR TRANSISTOR AND INTEGRATION INTO A STANDARD CMOS FLOW Public/Granted day:2010-03-18
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