Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level

Invention Grant

US07923757B2 Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level 有权

Title translation: 半导体器件和相关布局具有沿着至少五个相等间距的栅极电极限定的线形栅电极，栅电极连接通过单互连级

Please log in to see more content

Patent Title: Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level
Patent Title (中): 半导体器件和相关布局具有沿着至少五个相等间距的栅极电极限定的线形栅电极，栅电极连接通过单互连级
Application No.: US12563066

Application Date: 2009-09-18
Publication No.: US07923757B2

Publication Date: 2011-04-12
Inventor: Scott T. Becker , Michael C. Smayling
Applicant: Scott T. Becker , Michael C. Smayling
Applicant Address: US CA Los Gatos
Assignee: Tela Innovations, Inc.
Current Assignee: Tela Innovations, Inc.
Current Assignee Address: US CA Los Gatos
Agency: Martine Penilla & Gencarella, LLP
Main IPC: H01L27/10
IPC: H01L27/10

Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level

Abstract:

A restricted layout region includes a diffusion level layout including p-type and n-type diffusion region layout shapes separated by a central inactive region. The diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract(Chinese):

限制布局区域包括扩散级别布局，包括由中心非活动区域分隔的p型和n型扩散区域布局形状。扩散区域布局形状相对于被定义为平分扩散级布局的中心线以非对称的方式定义。栅极电极层布局被定义为包括仅在第一平行方向上延伸的线性布局特征。在第一并行方向上共享共同的范围的相邻的线性布局特征被跨越栅电极级布局基本上相等的端到端间隔隔开，并且被最小化到半导体器件允许的程度制造能力。栅电极级布局包括沿着沿着第一并行方向的至少四个不同的线段限定的线性布局特征。限制布局区域对应于单元布局的整个栅电极层。

Public/Granted literature

US20100011331A1 Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions Public/Granted day:2010-01-14

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L27/00	由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件（其零部件入H01L23/00，H01L29/00至H01L51/00；由多个单个固态器件组成的组装件入H01L25/00）
H01L27/02	.包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的；包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的
H01L27/04	..其衬底为半导体的
H01L27/10	...在重复结构中包括有多个独立组件的