Invention Grant
US07923847B2 Semiconductor system-in-a-package containing micro-layered lead frame
有权
包含微层引线框架的半导体系统级封装
- Patent Title: Semiconductor system-in-a-package containing micro-layered lead frame
- Patent Title (中): 包含微层引线框架的半导体系统级封装
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Application No.: US12334267Application Date: 2008-12-12
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Publication No.: US07923847B2Publication Date: 2011-04-12
- Inventor: Manolito Galera , Leocadio Morona Alabin
- Applicant: Manolito Galera , Leocadio Morona Alabin
- Applicant Address: US CA
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US CA
- Agency: Kirton & McConkie
- Agent Kenneth E. Horton
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
Semiconductor packages that contain a system-in-a-package and methods for making such packages are described. The semiconductor packages contain a first semiconductor die resting on a middle of a land pad array, a second die disposed over the first die and resting on routing leads that are connected to the land pad array, a third die resting on the backside of the second die and connected to the land pad array by wire bonds, and a passive device and/or a discrete device resting on device pads. The packages also contain thermal pads which operate as a heat sink. The land pad array is formed from etching the leadframe. The semiconductor packages have a full land pad array with a thin package size while having a system-in-a-package design. Other embodiments are also described.
Public/Granted literature
- US20100052121A1 SEMICONDUCTOR SYSTEM-IN-A-PACKAGE CONTAINING MICRO-LAYERED LEAD FRAME Public/Granted day:2010-03-04
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