Invention Grant
- Patent Title: Evaluation board and failure location detection method
- Patent Title (中): 评估板和故障定位检测方法
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Application No.: US12050453Application Date: 2008-03-18
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Publication No.: US07924022B2Publication Date: 2011-04-12
- Inventor: Hiroyuki Fujimoto
- Applicant: Hiroyuki Fujimoto
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2007-071679 20070319
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G01R31/28

Abstract:
An evaluation board, on which is mounted a chip to be evaluated is provided. Particularly, the evaluation board includes a monitoring window for monitoring a power supply part, a ground part, and a surface of the chip, a first signal input part for inputting signals to the chip, and a second signal input part for inputting signals to the chip, wherein the second signal input part is placed as to sandwich said monitoring window between itself and the first signal input part.
Public/Granted literature
- US20080231287A1 EVALUATION BOARD AND FAILURE LOCATION DETECTION METHOD Public/Granted day:2008-09-25
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