Invention Grant
US07924052B1 Field programmable gate array architecture having Clos network-based input interconnect
有权
具有基于Clos网络的输入互连的现场可编程门阵列结构
- Patent Title: Field programmable gate array architecture having Clos network-based input interconnect
- Patent Title (中): 具有基于Clos网络的输入互连的现场可编程门阵列结构
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Application No.: US12361835Application Date: 2009-01-29
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Publication No.: US07924052B1Publication Date: 2011-04-12
- Inventor: Wenyi Feng , Jonathan Greene , Sinan Kaptanoglu
- Applicant: Wenyi Feng , Jonathan Greene , Sinan Kaptanoglu
- Applicant Address: US CA Mountain View
- Assignee: Actel Corporation
- Current Assignee: Actel Corporation
- Current Assignee Address: US CA Mountain View
- Agency: Lewis and Roca LLP
- Main IPC: H01L25/00
- IPC: H01L25/00
Abstract:
A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.
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