Invention Grant
- Patent Title: Semiconductor integrated circuit device, pattern detection method and serial-parallel conversion method
- Patent Title (中): 半导体集成电路器件,模式检测方法和串并转换方法
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Application No.: US12246866Application Date: 2008-10-07
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Publication No.: US07924185B2Publication Date: 2011-04-12
- Inventor: Hiroto Fukuhisa
- Applicant: Hiroto Fukuhisa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Priority: JP2007-264733 20071010
- Main IPC: H03M9/00
- IPC: H03M9/00

Abstract:
A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock generation section configured to determine timing of output of the serial data held in the shift register on the basis of a result of this detection are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of a result of this detection, thus reducing the latency and achieving an improvement in communication speed and a reduction in circuit area.
Public/Granted literature
- US20090096644A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PATTERN DETECTION METHOD AND SERIAL-PARALLEL CONVERSION METHOD Public/Granted day:2009-04-16
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