In a successive approximation-type A/D converter, an S/H circuit samples and holds an analog input voltage. A D/A converter section receives current digital data corresponding to a current search voltage range, and outputs a plurality of comparison voltages based on the current digital data. A comparator section performs parallel comparison in which the held analog input voltage is compared with each of the plurality of comparison voltages. A successive approximation register section outputs digital data for a next search voltage range within the current search voltage range as the current digital data to the digital-to-analog converter section based on a result of the parallel comparison using the current search voltage range. A timing control circuit generates a switching signal from the parallel comparison to a redundant comparison such that the redundant comparison is performed.