Invention Grant
- Patent Title: Nonvolatile semiconductor memory, and method for reading data
- Patent Title (中): 非易失性半导体存储器以及读取数据的方法
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Application No.: US12458227Application Date: 2009-07-06
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Publication No.: US07924612B2Publication Date: 2011-04-12
- Inventor: Masahiko Kashimura
- Applicant: Masahiko Kashimura
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: RENESAS Electronics Corporation
- Current Assignee: RENESAS Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-181143 20080711
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
A nonvolatile semiconductor memory includes a memory cell, a first gate control circuit that is coupled to the memory cell, and a second gate control circuit that is coupled to the memory cell. The memory cell includes a first gate electrode that is formed above a channel region in a semiconductor substrate, a second gate electrode that is formed beside the first gate electrode, and that is capacitively coupled with the first gate electrode through a first insulating layer, and a charge trapping layer that is formed between the channel region and the second gate electrode, and that includes a second insulating layer for trapping a charge. Data stored in a memory cell transistor including the second gate electrode changes depending on an amount of the charge trapped in the charge trapping layer. The first gate control circuit applies a potential to the first gate electrode, when reading the data stored in the memory cell transistor. The second gate control circuit brings the second gate electrode into a floating state, when the potential is applied to the first gate electrode.
Public/Granted literature
- US20100118609A1 Nonvolatile semiconductor memory, and method for reading data Public/Granted day:2010-05-13
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