Invention Grant
US07924619B2 Programming method to reduce word line to word line breakdown for NAND flash
有权
用于减少NAND闪存字线到字线的编程方法
- Patent Title: Programming method to reduce word line to word line breakdown for NAND flash
- Patent Title (中): 用于减少NAND闪存字线到字线的编程方法
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Application No.: US12502537Application Date: 2009-07-14
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Publication No.: US07924619B2Publication Date: 2011-04-12
- Inventor: Seiichi Aritome
- Applicant: Seiichi Aritome
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/06 ; G11C16/12 ; G11C7/02 ; G11C8/08

Abstract:
A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage differences between the word lines of the memory cell string or array during a programming cycle. This allows the word line to word line voltage differential to be reduced and thus decreases the likelihood of breakdown or punch through of the insulator materials placed between the adjacent word lines.
Public/Granted literature
- US20090273979A1 PROGRAMMING METHOD TO REDUCE WORD LINE TO WORD LINE BREAKDOWN FOR NAND FLASH Public/Granted day:2009-11-05
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