Invention Grant
- Patent Title: Implementing boosted wordline voltage in memories
- Patent Title (中): 在存储器中实现提升的字线电压
-
Application No.: US12389420Application Date: 2009-02-20
-
Publication No.: US07924633B2Publication Date: 2011-04-12
- Inventor: Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
- Applicant: Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joan Pennington
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.
Public/Granted literature
- US20100214859A1 Implementing Boosted Wordline Voltage in Memories Public/Granted day:2010-08-26
Information query