Clock synchronization resistance is improved against selectivity fading without degrading the stability of clock phase synchronization control. Clock phase detector 7, which forms part of a clock reproduction PLL, is preceded by orthogonal component equalizer 6 for removing only orthogonal component interference wave not affecting the clock regeneration, thereby assuring an opening of an eye pattern and maintaining the gain of clock phase detector 7 without erasing the clock phase information. Accordingly, even when inter-symbol interference is caused in a received signal by selectivity fading or the like, part of the interference component can be erased to keep the opening of the eye pattern wide. Thus, the clock synchronization resistance can be improved against the selectivity fading without degrading the stability of the clock phase synchronization control.