A memory controller (1) writes data continuously to a first and a second blocks (20A), (20B) which are provided by dividing a memory region of a nonvolatile memory (2), and reads the data therefrom. The controller includes: a first writer (12A) which writes data to the first block (20A); and a second writer (12B) which writes data to the second block (20B) after completion of the writing by the first writer (12A) and a lapse of a waiting time generally equal to a length of time necessary for a power breakdown to drop a power source voltage down to a voltage value to at least disable the writing of data to the memory region.