Invention Grant
- Patent Title: Method of fabricating field effect transistors with different gate widths
- Patent Title (中): 制造栅极宽度不同的场效晶体管的方法
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Application No.: US12817508Application Date: 2010-06-17
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Publication No.: US07927941B2Publication Date: 2011-04-19
- Inventor: Hiroshi Nomura , Takashi Saiki , Tsunehisa Sakoda
- Applicant: Hiroshi Nomura , Takashi Saiki , Tsunehisa Sakoda
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Fujitsu Patent Center
- Priority: JP2005-183920 20050623
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/148

Abstract:
Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.
Public/Granted literature
- US20100255668A1 Field effect transistors with different gate widths Public/Granted day:2010-10-07
Information query
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