Invention Grant
- Patent Title: Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
- Patent Title (中): 包括金属到半导体超晶格界面层的半导体器件及相关方法
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Application No.: US12018255Application Date: 2008-01-23
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Publication No.: US07928425B2Publication Date: 2011-04-19
- Inventor: Kalipatnam Vivek Rao
- Applicant: Kalipatnam Vivek Rao
- Applicant Address: US MA Waltham
- Assignee: Mears Technologies, Inc.
- Current Assignee: Mears Technologies, Inc.
- Current Assignee Address: US MA Waltham
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Main IPC: H01L29/06
- IPC: H01L29/06

Abstract:
A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
Public/Granted literature
- US20080179588A1 SEMICONDUCTOR DEVICE INCLUDING A METAL-TO-SEMICONDUCTOR SUPERLATTICE INTERFACE LAYER AND RELATED METHODS Public/Granted day:2008-07-31
Information query
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