Invention Grant
US07928514B2 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics
有权
在具有高k电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制
- Patent Title: Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics
- Patent Title (中): 在具有高k电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制
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Application No.: US12355368Application Date: 2009-01-16
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Publication No.: US07928514B2Publication Date: 2011-04-19
- Inventor: Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
- Applicant: Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
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