Invention Grant
- Patent Title: Post passivation interconnection schemes on top of the IC chips
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Application No.: US12019635Application Date: 2008-01-25
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Publication No.: US07928576B2Publication Date: 2011-04-19
- Inventor: Mou-Shiung Lin
- Applicant: Mou-Shiung Lin
- Applicant Address: TW Hsinchu
- Assignee: Megica Corporation
- Current Assignee: Megica Corporation
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
Public/Granted literature
- US20080116581A1 POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS Public/Granted day:2008-05-22
Information query
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