Invention Grant
- Patent Title: Memory device performing write leveling operation
- Patent Title (中): 执行写平均操作的内存设备
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Application No.: US11819815Application Date: 2007-06-29
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Publication No.: US07929355B2Publication Date: 2011-04-19
- Inventor: Ji-Eun Jang
- Applicant: Ji-Eun Jang
- Applicant Address: KR Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2007-0000424 20070103
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/10

Abstract:
A memory device includes a multiplexing unit, a pipe latch unit, and an output driver. The multiplexing unit outputs data input from global input/output lines in a normal mode and outputs write leveling data in a writing leveling mode being entered in response to a write leveling signal. The pipe latch unit latches the data outputted from the multiplexing unit and outputting the latched data. The output driver outputs the latched data outputted from the pipe latch unit.
Public/Granted literature
- US20090016119A1 Memory device performing write leveling operation Public/Granted day:2009-01-15
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