Invention Grant
- Patent Title: Semiconductor device comprising circuit substrate with inspection connection pads and manufacturing method thereof
- Patent Title (中): 包括具有检查连接焊盘的电路基板的半导体器件及其制造方法
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Application No.: US12079259Application Date: 2008-03-26
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Publication No.: US07932517B2Publication Date: 2011-04-26
- Inventor: Yuji Negishi
- Applicant: Yuji Negishi
- Applicant Address: JP Tokyo
- Assignee: Casio Computer Co., Ltd.
- Current Assignee: Casio Computer Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz, Goodman & Chick, PC
- Priority: JP2007-087662 20070329
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof, respectively. A second circuit substrate is provided on a lower side of the first circuit substrate, the second circuit substrate having an opening which exposes part of the first circuit substrate, the second circuit substrate also having, on the lower surface side thereof, a plurality of external-connection connection pads and a plurality of test connection pads connected to the lower wiring lines. A first semiconductor construct is disposed on the lower side of the first circuit substrate within the opening of the second circuit substrate, the first semiconductor construct having a plurality of external connection electrodes connected to the lower wiring lines. A third circuit substrate and/or an electronic component is provided on an upper side of the first circuit substrate and connected to the upper wiring lines.
Public/Granted literature
Information query
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