A regulator circuit and a method of generating a stable, low-ripple output, step-up or step-down voltage are disclosed. A low ESR (Equivalent Series Resistance) output capacitor is employed to provide low output voltage ripple. A voltage, −VESRi, is generated using information based on an input voltage and the output voltage. −VESRi is coupled onto an intermediate reference voltage generated by an integrator based on the output voltage and a constant reference voltage, to form another voltage, VREFi. VREFi is coupled to an input of a feedback comparator, instead of a plain constant reference voltage, to modulate the duty cycle of a main switch. The output voltage is inputted as a feedback signal to another input of the feedback comparator. −VESRi, is generated using information based on an input voltage and the output voltage in such a way that output voltage is stable without sub-harmonic oscillation.