A power insulated gate field effect transistor has main cells (2) controlled by a main cell insulated gate and sense cells (4) controlled by a sense cell insulated gate. A sample and hold circuit (10, 50) is arranged to operate in a plurality of states including at least one sample state and a hold state to sense the current flowing through the sense cells (4) when in the at least one sample state but not in the hold state. The sample states may be used in a feedback loop to control a drive amplifier (20) driving the gates of the main and sense cells (2,4) and/or to mirror the current in the sense cells (4) on a measurement output terminal (58).