Invention Grant
US07933102B2 Circuit configurations to reduce snapback of a transient voltage suppressor
有权
电路配置,以减少瞬态电压抑制器的快速恢复
- Patent Title: Circuit configurations to reduce snapback of a transient voltage suppressor
- Patent Title (中): 电路配置,以减少瞬态电压抑制器的快速恢复
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Application No.: US12454333Application Date: 2009-05-15
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Publication No.: US07933102B2Publication Date: 2011-04-26
- Inventor: Shekar Mallikararjunaswamy
- Applicant: Shekar Mallikararjunaswamy
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Ltd.
- Current Assignee: Alpha & Omega Semiconductor, Ltd.
- Current Assignee Address: US CA Sunnyvale
- Agent Bo-In Lin
- Main IPC: H02H9/00
- IPC: H02H9/00

Abstract:
This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.
Public/Granted literature
- US20090262476A1 Circuit configurations to reduce snapback of a transient voltage suppressor Public/Granted day:2009-10-22
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