Invention Grant
US07933161B2 Memory device configured to refresh memory cells in a power-down state
有权
配置为在掉电状态下刷新存储单元的内存设备
- Patent Title: Memory device configured to refresh memory cells in a power-down state
- Patent Title (中): 配置为在掉电状态下刷新存储单元的内存设备
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Application No.: US11509057Application Date: 2006-08-24
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Publication No.: US07933161B2Publication Date: 2011-04-26
- Inventor: Hideaki Miyamoto , Shigeharu Matsushita
- Applicant: Hideaki Miyamoto , Shigeharu Matsushita
- Applicant Address: US DE Wilmington
- Assignee: Patrenella Capital Ltd., LLC
- Current Assignee: Patrenella Capital Ltd., LLC
- Current Assignee Address: US DE Wilmington
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Priority: JP2005-241943 20050824
- Main IPC: G11C7/20
- IPC: G11C7/20
Abstract:
A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads data from and rewrites data in the memory cell in a power-down state.
Public/Granted literature
- US20070047363A1 Memory Public/Granted day:2007-03-01
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