Invention Grant
- Patent Title: Row addressing
- Patent Title (中): 行寻址
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Application No.: US12125598Application Date: 2008-05-22
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Publication No.: US07933162B2Publication Date: 2011-04-26
- Inventor: Takuya Nakanishi , Takumi Nasu , Yoshinori Fujiwara
- Applicant: Takuya Nakanishi , Takumi Nasu , Yoshinori Fujiwara
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder P.C.
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C7/00 ; G06F9/26 ; G06F9/34

Abstract:
Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed. Further embodiments include a method for receiving a row address for a row in a memory section including a non-2^n number of normal rows and mapping the row address to a redundant row address by substracting a value from the row address.
Public/Granted literature
- US20090290440A1 Row Addressing Public/Granted day:2009-11-26
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