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US07934031B2 Reshuffled communications processes in pipelined asynchronous circuits 有权
流水线异步电路中的重新整合的通信过程

Reshuffled communications processes in pipelined asynchronous circuits
Abstract:
An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.
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