A data processing apparatus contains a first bus connected to a first memory, a first central processing unit (CPU) being accessible to the first memory via the first bus, a first Direct Memory Access (DMA) controller being accessible to the first memory via the first bus, and a monitor circuit connected to the first bus and monitoring addresses transferred on the first bus. The addresses transferred on the first bus are transmitted from the first DMA controller to the first memory via the first bus. The monitor circuit compares the address transferred on the first bus with a preset monitor target address. The CPU acquires the comparison results by the monitor circuit. If the comparison results show an address match, then the CPU accesses the first memory. The CPU can in this way access the first memory at a correct timing.