Invention Grant
- Patent Title: Method and apparatus for performing logic built-in self-testing of an integrated circuit
- Patent Title (中): 用于执行集成电路内置自检的逻辑的方法和装置
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Application No.: US12133830Application Date: 2008-06-05
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Publication No.: US07934134B2Publication Date: 2011-04-26
- Inventor: Donato O. Forlenza , Orazio P. Forlenza , Bryan J. Robbins , Phong T. Tran
- Applicant: Donato O. Forlenza , Orazio P. Forlenza , Bryan J. Robbins , Phong T. Tran
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Dillon & Yudell LLP
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.
Public/Granted literature
- US20090307548A1 METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT Public/Granted day:2009-12-10
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