A method of a layout a semiconductor circuit has obtaining transistor characteristic information on the basis of layout information about regions formed with transistors, obtaining a polynomial expression representing a relationship between characteristic values of a circuit including of the transistors and the transistor characteristic information, calculating a plurality of characteristic values corresponding to plural sets of transistor characteristic information by use of the polynomial expression, selecting part of the plurality of characteristic values on the basis of a restriction about the characteristic values, the layout information or the transistor characteristic information; and obtaining the transistor characteristic information or the layout information corresponding to the selected characteristic values.