Invention Grant
- Patent Title: Method of forming shielded gate FET with self-aligned features
- Patent Title (中): 形成具有自对准特征的屏蔽栅极FET的方法
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Application No.: US12480031Application Date: 2009-06-08
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Publication No.: US07935561B2Publication Date: 2011-05-03
- Inventor: Chanho Park
- Applicant: Chanho Park
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L23/60
- IPC: H01L23/60
Abstract:
A method for forming a shielded gate field effect transistor includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A shield electrode is formed in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric. A gate electrode recessed in each trench is formed over the shield electrode, the gate electrode being insulated from the shield electrode. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.
Public/Granted literature
- US20090246923A1 Method of Forming Shielded Gate FET with Self-aligned Features Public/Granted day:2009-10-01
Information query
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