Invention Grant
- Patent Title: Components, methods and assemblies for stacked packages
- Patent Title (中): 堆叠包的组件,方法和装配
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Application No.: US11975996Application Date: 2007-10-23
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Publication No.: US07935569B2Publication Date: 2011-05-03
- Inventor: Kyong-Mo Bang , David Gibson , Young-Gon Kim , John B. Riley, III
- Applicant: Kyong-Mo Bang , David Gibson , Young-Gon Kim , John B. Riley, III
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.
Public/Granted literature
- US20080042274A1 Components, methods and assemblies for stacked packages Public/Granted day:2008-02-21
Information query
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