Invention Grant
US07935571B2 Through substrate vias for back-side interconnections on very thin semiconductor wafers 有权
通过用于非常薄的半导体晶片上的背面互连的衬底通孔

Through substrate vias for back-side interconnections on very thin semiconductor wafers
Abstract:
Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18′); etching (104) via cavities (29) partly through the wafer (18′) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18′) with its front side (35) facing a support structure (40); thinning (107) the wafer (18′) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.) of the filled vias; removing (109) the support structure (40) and separating the individual device or IC assemblies (48) so as to be available for mounting (110) on a further circuit board, tape or larger circuit (50).
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