Invention Grant
US07935577B2 Method for forming shielded gate field effect transistor using spacers
有权
用间隔物形成屏蔽栅场效应晶体管的方法
- Patent Title: Method for forming shielded gate field effect transistor using spacers
- Patent Title (中): 用间隔物形成屏蔽栅场效应晶体管的方法
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Application No.: US12344859Application Date: 2008-12-29
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Publication No.: US07935577B2Publication Date: 2011-05-03
- Inventor: Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley
- Applicant: Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L21/8232
- IPC: H01L21/8232 ; H01L21/84 ; H01L21/00 ; H01L21/336
Abstract:
A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.
Public/Granted literature
- US20090111231A1 Method for Forming Shielded Gate Field Effect Transistor Using Spacers Public/Granted day:2009-04-30
Information query
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