Invention Grant
- Patent Title: Enhanced transistor performance by non-conformal stressed layers
- Patent Title (中): 通过非保形应力层增强晶体管性能
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Application No.: US11682554Application Date: 2007-03-06
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Publication No.: US07935588B2Publication Date: 2011-05-03
- Inventor: Bruce B. Doris , Xiao Hu Liu
- Applicant: Bruce B. Doris , Xiao Hu Liu
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent George Sai-Halasz; Louis J. Percello
- Main IPC: H01L21/8234
- IPC: H01L21/8234

Abstract:
NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching.
Public/Granted literature
- US20080217663A1 Enhanced Transistor Performance by Non-Conformal Stressed Layers Public/Granted day:2008-09-11
Information query
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