Invention Grant
- Patent Title: Enhanced stress for transistors
- Patent Title (中): 晶体管增强应力
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Application No.: US12111214Application Date: 2008-04-29
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Publication No.: US07935589B2Publication Date: 2011-05-03
- Inventor: Lee Wee Teo , Jae Gon Lee , Shyue Seng Tan , Elgin Quek
- Applicant: Lee Wee Teo , Jae Gon Lee , Shyue Seng Tan , Elgin Quek
- Applicant Address: SG Singapore
- Assignee: Chartered Semiconductor Manufacturing, Ltd.
- Current Assignee: Chartered Semiconductor Manufacturing, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Horizon IP Pte Ltd
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234

Abstract:
A transistor disposed on a substrate includes a gate, spacers on gate sidewalls, and diffusion regions adjacent to the gate. Silicide contacts on the diffusion regions are displaced from the spacers by a distance G. Stressors may be provided in the diffusion region to induce a first stress in the channel region of the transistor.
Public/Granted literature
- US20090267117A1 ENHANCED STRESS FOR TRANSISTORS Public/Granted day:2009-10-29
Information query
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