Invention Grant
US07935591B2 Method for fabricating PMOS transistor and method for forming dual gate using the same
有权
制造PMOS晶体管的方法及使用其形成双栅的方法
- Patent Title: Method for fabricating PMOS transistor and method for forming dual gate using the same
- Patent Title (中): 制造PMOS晶体管的方法及使用其形成双栅的方法
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Application No.: US12346492Application Date: 2008-12-30
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Publication No.: US07935591B2Publication Date: 2011-05-03
- Inventor: Kyoung Bong Rouh , Choon Hwan Kim , Il Cheol Rho
- Applicant: Kyoung Bong Rouh , Choon Hwan Kim , Il Cheol Rho
- Applicant Address: KR Icheon-si
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-si
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: KR10-2008-0111581 20081111
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber.
Public/Granted literature
- US20100120240A1 METHOD FOR FABRICATING PMOS TRANSISTOR AND METHOD FOR FORMING DUAL GATE USING THE SAME Public/Granted day:2010-05-13
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