Invention Grant
- Patent Title: Method of manufacturing semiconductor device having of spacer gate structure
- Patent Title (中): 具有隔离栅结构的半导体器件的制造方法
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Application No.: US11980554Application Date: 2007-10-31
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Publication No.: US07935592B2Publication Date: 2011-05-03
- Inventor: Takashi Watanabe
- Applicant: Takashi Watanabe
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2006-297774 20061101
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
In a case of using a silicon nitride film as an offset spacer for forming an extension region of a transistor, an oxide protective surface is formed by oxygen plasma processing on the surface of the silicon nitride film.
Public/Granted literature
- US20080099859A1 Method of manufacturing semiconductor device having of spacer gate structure Public/Granted day:2008-05-01
Information query
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