Invention Grant
- Patent Title: Method for manufacturing semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US11581346Application Date: 2006-10-17
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Publication No.: US07935595B2Publication Date: 2011-05-03
- Inventor: Shigeru Shiratake
- Applicant: Shigeru Shiratake
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory Inc.
- Current Assignee: Elpida Memory Inc.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-313661 20051028
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (11s) in a peripheral circuit region PE is covered by a protective film (12), a gate trench (18) is formed in a memory cell region M, after which a gate insulating film (19) that is thicker than the gate insulating film (11s) is formed on an inner wall of the gate trench (18) in a state in which the gate insulating film (11s) of the peripheral circuit region PE is still covered by the protective film (12).
Public/Granted literature
- US20070096204A1 Method for manufacturing semiconductor device Public/Granted day:2007-05-03
Information query
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