Invention Grant
- Patent Title: Semiconductor device isolation structures
- Patent Title (中): 半导体器件隔离结构
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Application No.: US11604958Application Date: 2006-11-28
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Publication No.: US07935610B2Publication Date: 2011-05-03
- Inventor: Sukesh Sandhu
- Applicant: Sukesh Sandhu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. An isolation region may be interposed between the first integrated device region and the second integrated device region. The isolation region may include an isolation recess that projects into the substrate to a first predetermined depth, and that may be extended to a second predetermined depth.
Public/Granted literature
- US20080124888A1 Semiconductor device isolation structures Public/Granted day:2008-05-29
Information query
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