Invention Grant
- Patent Title: Semiconductor scheme for reduced circuit area in a simplified process
- Patent Title (中): 减少电路面积的半导体方案
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Application No.: US11876230Application Date: 2007-10-22
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Publication No.: US07935629B2Publication Date: 2011-05-03
- Inventor: Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
- Applicant: Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Robert R. Williams
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
Public/Granted literature
- US20080102627A1 Semiconductor Scheme for Reduced Circuit Area in a Simplified Process Public/Granted day:2008-05-01
Information query
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