Invention Grant
US07935997B2 Low resistance peripheral contacts while maintaining DRAM array integrity
有权
低电阻外围触点,同时保持DRAM阵列的完整性
- Patent Title: Low resistance peripheral contacts while maintaining DRAM array integrity
- Patent Title (中): 低电阻外围触点,同时保持DRAM阵列的完整性
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Application No.: US11612588Application Date: 2006-12-19
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Publication No.: US07935997B2Publication Date: 2011-05-03
- Inventor: Terrence McDaniel
- Applicant: Terrence McDaniel
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
An apparatus having low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide in contact structures of the peripheral logic circuitry areas and physical vapor deposition to provide a metal mode (metallic) titanium layer in contact with the poly plugs in the memory cell array area of a semiconductor device, for example, a DRAM memory device according to the present invention. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the present of titanium silicide, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.
Public/Granted literature
- US20070158749A1 LOW RESISTANCE PERIPHERAL CONTACTS WHILE MAINTAINING DRAM ARRAY INTEGRITY Public/Granted day:2007-07-12
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