Invention Grant
US07936000B2 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
有权
用于高密度，低电压逻辑和存储器阵列的垂直环绕栅极场效应晶体管
- Patent Title: Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
- Patent Title (中): 用于高密度，低电压逻辑和存储器阵列的垂直环绕栅极场效应晶体管
-
Application No.: US12417128Application Date: 2009-04-02
-
Publication No.: US07936000B2Publication Date: 2011-05-03
- Inventor: Sanh D. Tang , Robert J. Burke , Anand Srinivasan
- Applicant: Sanh D. Tang , Robert J. Burke , Anand Srinivasan
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dickstein Shapiro LLP
- Main IPC: H01L29/92
- IPC: H01L29/92 ; H01L27/10 ; H01L29/786
Abstract:
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
Public/Granted literature
- US20090207649A1 VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY Public/Granted day:2009-08-20
Information query
IPC分类:
