Invention Grant
- Patent Title: LDMOS with self aligned vertical LDD backside drain
- Patent Title (中): LDMOS具有自对准垂直LDD背面排水
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Application No.: US12425349Application Date: 2009-04-16
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Publication No.: US07936007B2Publication Date: 2011-05-03
- Inventor: Bruce D. Marchant , Daniel M. Kinzer
- Applicant: Bruce D. Marchant , Daniel M. Kinzer
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kilpatrick Townsend and Stockton LLP
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94

Abstract:
A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region.
Public/Granted literature
- US20100264490A1 LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN Public/Granted day:2010-10-21
Information query
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