Invention Grant
- Patent Title: Charge balance techniques for power devices
- Patent Title (中): 电力设备的电荷平衡技术
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Application No.: US12562025Application Date: 2009-09-17
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Publication No.: US07936013B2Publication Date: 2011-05-03
- Inventor: Christopher Boguslaw Kocon
- Applicant: Christopher Boguslaw Kocon
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
A vertically-conducting charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state, and a non-active perimeter region surrounding the active area. No current flows along the vertical dimension through the non-active perimeter region when the plurality of cells is biased in the conducting state. Strips of p pillars and strips of n pillars are arranged in an alternating manner. The strips of p pillars have a depth extending along the vertical dimension, a width, and a length. The strips of p and n pillars extend through both the active area and the non-active perimeter region along a length of a die that contains the semiconductor power device. The length of the die extends parallel to the length of the strips of p pillars. Each of the strips of p pillars includes a plurality of discontinuities forming portions of a plurality of strips of n regions. The plurality of strips of n regions extends in the non-active perimeter region perpendicular to the length of the die.
Public/Granted literature
- US20100006927A1 Charge Balance Techniques for Power Devices Public/Granted day:2010-01-14
Information query
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